A logic-simulation model of an electronic circuit is a diagnostic tool used by a logical-simulator to accurately mimic the logic and timing behavior of the circuit. The purpose of using such a model is to verify both logic and timing behavior of an operational electronic system containing the circuit. The internal operation and internal structure of a simulation model need not be similar to that of the actual circuit being simulated. However, the logical and timing behavior of the simulation model, as externally observed during simulation, must be identical to that of the actual circuit in its real environment.
Simulation models can be divided into three major classes: behavioral models, structural models, and hardware models. Behavioral models represent device behavior by using code written in an algorithmic language such as "C." They are compiled and linked with a simulator and run on a general-purpose computer. Structural models mimic the actual internal structure of a device; they generally run on either general-purpose or special-purpose computers. Behavioral models and structural models are both represented with software and are therefore also called "software models."
A hardware modeling system ("HMS") couples an actual "known-good" physical device (called a "hardware modeling element" or "HME") with a simulator; the physical device is used to model its own behavior during simulation. When the simulator requests a device evaluation, the HMS formats the inputs received from the simulator, applies the inputs to the physical device, measures device behavior, and returns the resulting outputs plus timing information to the simulator. The timing information is generally obtained from a table in a text file called a "software shell," which contains a representation of the data-book delays.
Before hardware modeling systems became available, logic simulation models were generally software models. Software models are practical for low-complexity circuits, but software models of complex very large scale integration ("VLSI") circuits have numerous disadvantages. For example, they may be costly and time consuming to develop, they may be inaccurate, they may be difficult to check, they may execute quite slowly, and they may not be portable between simulators.
In an attempt to address these problems, Valid Logic Systems in 1984 introduced the Realchip.TM. hardware modeling system which provided an alternative to software simulation models for complex circuits. Realchip is a trademark of Valid Logic Systems. Valid Logic Systems' Realchip.TM. system was the basis of two U.S. Pat. Nos. 4,590,581, and 4,635,218, which issued in 1987.
Similar hardware modeling systems were subsequently introduced by Mentor Graphics ("HML"), Daisy Systems ("PMX"), GenRad ("HiChip"), Teradyne ("DataSource"), Cadnetix ("CDX-7000"), HHB Systems ("CATS"), and Tektronix ("TurboChip"). The Mentor Graphics HML hardware modeling system formed the basis for U.S. Pat. No. 4,744,084, which issued in 1988 and claimed improvements over the Realchip.TM. system.
Users have attempted to apply these prior-art hardware modeling systems in several different ways in the design and test of electronic systems. The primary attempted application of prior-art hardware modeling systems is modeling standard devices and existing ASICs during simulation of electronic systems. In this mode, the designer may run real diagnostic software on the simulated system, verifying the operation of the entire system working together as if it had been prototyped.
Another attempted application of prior-art hardware modeling systems is to use an entire existing subsystem, such as a PC board, as an HME, verifying the operation of the entire system containing the PC board as if it had been prototyped.
Another attempted application of prior-art hardware modeling systems is to debug embedded system software and microcode before fabrication of the prototype system.
Another attempted application of prior-art hardware modeling systems is to examine the behavior of existing standard devices and ASICs for which specifications may be inadequate or inaccurate. In this mode, the design engineer uses the device in question as an HME, stimulating and observing it with the simulator's normal user interface. This enables him to directly and easily answer questions about its behavior while the system design progresses.
Another attempted application of prior-art hardware modeling systems is in ASIC design. Many ASICs which are designed and verified in isolation do not operate properly within the target system. A hardware modeling system can help to solve this problem because it gives the designer access to full-function models of all the complex devices in the embedding system and enables him to simulate the entire system together before ASIC fabrication.
Another attempted application of prior-art hardware modeling systems is for functional verification of prototype ASICs. In this mode, the engineer fixtures the prototype ASIC as an HME, uses the resulting hardware model in place of the earlier gate-level model, and runs the same simulation test cases that were run during the design phase.
Although the prior-art hardware modeling systems enjoyed some commercial success, they suffer from a number of serious limitations with respect to these applications. One limitation of prior-art hardware modeling systems is that they lack the capability to be easily integrated with simulators from multiple different vendors. Therefore, in general, each one works with only one or at most a small set of simulators and cannot be accessed concurrently by multiple simulators running on multiple host platforms. Thus, designers using simulators from multiple vendors may need to buy multiple hardware modeling systems.
Also, prior-art hardware modeling systems are limited in their support for ASICs. For example, state-of-art ASICs have very high pin counts, and prior-art hardware modeling systems do not directly support very-high-pin-count devices. Also, prior-art hardware modeling systems do not directly support the capture and replay of test vectors for ASIC prototype verification.
Also, prior-art hardware modeling systems do not support direct timing measurement of HME output delays. Direct timing measurement is important for the comprehensive verification of prototype ASICs. Direct timing measurement is also important to simplify creation of the shell software for new ASIC hardware models.
Also, prior-art hardware modeling systems have proven difficult to use due to requirements for custom pin wiring on device adapters, specialized initialization circuitry, and complex software shells.
Also, prior-art hardware modeling systems are generally not fully and easily configurable. Hardware modeling systems can be used in several distinct modes which require configuration of the modeler in different dimensions. For example, system-level simulation requires that the HMS be configured for a large number of devices simultaneously mounted; ASICs tend to have high pin counts, so modeling and verifying them requires support for high-pin-count devices; and simulating the execution of software on processor models requires deep pattern memory. Prior-art hardware modeling systems limited simultaneous configurability in these dimensions.
Also, prior-art modeling systems suffer from poor performance, particularly in round-trip access time from the simulator, and in pattern-presentation rate. Better performance in both areas is necessary to keep pace with faster simulators and workstations, and to properly refresh state-of-the-art high-speed dynamic devices so that correct results are obtained.
Also, prior-art hardware modeling systems suffer from limitations of the "pin electronics," which is the electronic circuitry used by the hardware modeling system to stimulate and sample the inputs, outputs, and bi-directional ("I/O") pins of the HME. For example, because of the primitive nature of the pin electronics in the prior-art hardware modeling systems, when certain types of integrated circuits, particularly those having feed-through paths connecting I/O pins, such as the 74ALS645 bi-directional bus buffer manufactured by Texas Instruments, are used as HMEs in such systems, the very process of electronically sampling some I/O pins of the integrated circuit may inadvertently stimulate the device and cause incorrect signal values to be sampled on other I/O or output pins. As a result, the hardware modeling system may return incorrect results to the workstation which is performing the simulation. Some users of prior-art hardware modeling systems refer to this problem as the "coupled-I/Os problem."
Also, in prior-art hardware modeling systems, generally at least two bits are stored in each stimulus pattern for each pin of the HME, e.g., one bit for the data value and one bit which can inhibit the HMS pin driver. Since memory for pattern storage is generally expensive, a system and associated method of use is needed for reducing the amount and, therefore, the cost of required pattern storage.
Also, prior-art hardware modeling systems suffer from other deficiencies due to inadequate pin electronics, such unreliability and a lack of capability to support multiple integrated circuit technologies (such as TTL and low-voltage CMOS). Because of the inability to support multiple integrated circuit technologies, some types of integrated circuits cannot be used as HMEs in prior-art hardware modeling systems.
Therefore, a need exists for an improved hardware modeling system, and a method which is directed toward solving and minimizing these and other problems of prior-art devices.